1. Field of the Invention
The present invention relates to a photosensitive cell reading method and device.
2. Discussion of the Related Art
FIG. 1 shows an example of a conventional device for reading a photosensitive cell 10 belonging to an array of cells arranged in rows and columns.
Cell 10 is formed of a photosensitive diode 12 having its anode connected to ground GND, and having its cathode connected to the source of a MOS-type N-channel transfer transistor 14. The drain of transistor 14 is connected to the source of a MOS-type N-channel reset transistor 16 having its drain connected to a source of a supply voltage VRT.
The gate of transfer transistor 14 is controlled by a voltage VTG. The gate of reset transistor 16 is controlled by a voltage VR. The drain of transistor 14 and the source of transistor 16 are connected to the cathode of a transfer diode 18 and to the gate of a transistor 20. Call VS the voltage at the gate of transistor 20, which is equal to the voltage across diode 18. The anode of diode 18 is connected to ground GND. The drain of transistor 20 is connected to the source of reference voltage VRT. The source of transistor 20 is connected to the drain of a read transistor 22. The source of read transistor 22 forms the output of cell 10. The gate of read transistor 22 is controlled by a voltage VREAD.
The source of transistor 22 is connected to a conductive column track 24. To each column of the array of photosensitive cells is associated a column conductive track which is connected to all cells 10 in the column.
To each column track is associated a read device 30. Read device 30 includes a first capacitor 32 having a terminal connected to ground GND and its other terminal connected to a track of column 24, via a first switch 33, and to the input of a first unity-gain impedance corrector 34. The output of first impedance corrector 34 provides a voltage V35 on a first output terminal 35 of device 30.
Device 30 includes a second capacitor 36 having a terminal connected to ground GND and its other terminal connected to column track 24, via a second switch 37, and to the input of a second unity-gain impedance corrector 38. The output of second impedance corrector 38 provides a voltage V39 on a second output terminal 39 of device 30.
Switches 33, 37 may be formed of MOS-type transistors operating as switches and having their gates respectively controlled by voltages V11 and V12. Impedance correctors 34, 38 may be formed of follower-assembled transistors.
A current source 40 is present on column track 24.
FIG. 2 shows a timing diagram of voltages at specific points of FIG. 1, illustrating a conventional method of reading of cell 10 by read device 30. Each step of the process is in fact simultaneously carried out for all the cells 10 in a same row. The read method will be described hereafter for a single cell 10.
On the abscissa axis are shown successive times t1 to t8. On the ordinate axis are shown different variation curves 50 to 56 of voltages at specific points of cell 10 and of read device 30 of FIG. 1.
Curve 50 shows voltage VS on the gate of transistor 20 and across diode 18. Curve 51 shows voltage VR applied to the gate of transistor 16. Curve 52 shows control voltage V11 of switch 33. Curve 53 shows voltage VTG applied to the gate of transistor 14. Curve 54 shows control voltage V12 of switch 37. Curve 55 shows voltage V35 on output terminal 35, and curve 56 shows voltage V39 on output terminal 39.
Diode 12 is a reverse-biased photosensitive diode. It behaves as a capacitor charged under an initial voltage, which discharges when exposed to a light source, the charge lost by diode 12 being a function of the received light intensity.
All along the read phase, voltage VREAD on the gate of transistor 22 is such that transistor 22 behaves as an on switch.
At time t1, voltage VR switches from a zero value to a positive value. Transistor 16 turns on. Voltage VRT is then applied across diode 18 which, as it is reverse biased, behaves as a capacitor. Voltage VS on the gate of transistor 20 is then equal to voltage VRT.
At time t2, voltage VR becomes zero again. Transistor 16 is then off. Voltage VS slightly drops due to a coupling between diode 18 and transistor 16.
At time t3, voltage V11 switches from a zero value to a positive value. Switch 33, which used to be off, turns on. Voltage V35, corresponding to the voltage across capacitor 32, is then equal to a constant value VREF which is a function of voltage VS.
At time t4, voltage V11 switches back to zero and switch 33 turns off. Capacitor 32 keeps between its terminals voltage VREF.
At time t5, voltage VTG switches from a zero value to a positive value. Transistor 14 turns on. Diode 18 then discharges into diode 12, which translates as a decrease in voltage VS. This decrease is representative of the amount of light received by diode 12.
At time t6, voltage VTG switches back to zero, and transistor 14 turns off. Voltage VS at the gate of transistor 20 remains steady.
At time t7, voltage V12 switches from a zero value to a positive value. Switch 37, which used to be off, turns on. Voltage V39, corresponding to the voltage across capacitor 36, is then equal to a constant voltage VPIX which is a function of voltage VS.
At time t8, voltage V12 switches back to zero and switch 37 turns off. Capacitor 36 keeps between its terminals voltage VPIX.
Difference VU between voltages VREF and VPIX is representative of the light intensity received by cell 10. Output terminals 35, 39 are connected to amplifiers or converters (not shown) enabling performing different processings on voltage VU.
The fact of considering voltage Vu to be useful enables suppressing the noise sampled on diode 18 upon disconnection from voltage VRT by transistor 16. Indeed, this noise reappears identically on both transistors VREF and VPIX, and is thus suppressed when the difference between these two voltages is calculated to obtain useful voltage VU.
Voltage VU however includes noise which originates from the read chain including transistors 20, 22, and current source 40. This noise is not suppressed or decreased by the previously-described read process.
Read device 30 is generally directly integrated at the level of the column having a width on the order of some ten micrometers. For want of room, it is not possible to directly include amplifiers in device 30. Said amplifiers must be placed downstream of read circuit 30 and thus amplify all the noises added downstream of read device 30. The presence of amplifiers is all the more necessary as the cell 10 of the type shown in FIG. 1 exhibits a reduced dynamic range since voltage VPIX can only vary between a voltage which depends on the maximum number of charges stored in diode 12 (which is variable according to the manufacturing process of diode 12 ) and a voltage VREF smaller than VRT. Typically, the difference between VREF and VPIX does not exceed 1 volt.
Further, the dissymmetry of impedance correctors 34, 38, results in an offset voltage which can be different for the correctors of the different columns Accordingly, voltages VU, obtained from cells belonging to two different columns having received the same light intensity, may be different. This may translate as the occurrence of vertical bars on an image calculated based on signals VU.